Discussions about way to go altera!

way to go Altera! On Sun, 26 Apr 2009 03:47:04 -0700 (PDT), Antti <Antti.Lukats@googlemail.com A while ago i did some research related to capacitive touch sensing, and was really surprised to see that this function is offered by Altera as ready made solution. today... Started by Antti on Sunday, April 26, 2009, 4 posts by 4 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): Hi Antti - Altera. Or altera? I have tried both methods with FPGA, but not used in products yet Antti and was really surprised to see that this function is offered by Altera as ready made solution.

Re: way to go Altera! On Mon, 27 Apr 2009 02:09:36 +0200, whygee <whygee@yg.yg hmmm cool, it gives me new ideas :-) -- http://ygdes.com / http://yasep.org Started by whygee on Monday, April 27, 2009, 3 posts by 3 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): Hi Antti - Altera recently released a webcast on capacitive. Antti.Lukats@googlemail.com On Apr 27, 3:09 am, whygee <why...@yg.yg didi or altera? I have tried both methods is offered by Altera as ready made solution.

Low-cost Altera FPGA roadmap On Mon, 13 Apr 2009 23:31:08 -0700 (PDT), acd <acd4usenet@lycos.de Since the Cyclone III is now 2 years on the market I wonder whether Altera's low-cost line is the Arria branch (with Arria II recently announced) or whether there will be Cyclone... Started by acd on Monday, April 13, 2009, 12 posts by 7 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): Way to go, Petter! On Apr 14, 12:35 am, Petter Gustad about next Altera thing to be flash based and have ColdFire hard core, but on the serious side the new Altera low cost family.... With abrasive comments about posting style.

Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell? On Thu, 28 May 2009 08:07:27 -0700 (PDT), Weng Tianxiang <wtxwtx@gmail.com Hi, I don't like to print download version of many documents. The download prints are huge and not easy to keep them in order. So that I bought Virtex-4 FPGA Handbook for... Started by Weng Tianxiang on Thursday, May 28, 2009, 10 posts by 5 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): For sure, either way is faster, more convenient, and overall cheaper. That I spent my $500 and did just that.

PLL and clock in altera cyclone 2 fpga On Fri, 19 Dec 2008 21:13:15 -0800, Jamie Morken <jmorken@shaw.ca Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to this block it will work properly, but... Started by Jamie Morken on Friday, December 19, 2008, 6 posts by 6 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): A much better way, however, to solve Your problem might be to create a clock that's twice second clock-cycle of Your 18 MHz clock (that's the "official way" to deal with those problems. In Your case.

Best way to approach FPGA Device Requirements When designing FPGA systems how can I estimate roughly the number of logic blocks a given task would require? Anyone have a rough order of magnitude on what I should expect for these comon devices?: UART packet deframer with CRC32 8 micro core I've seen... Started by Jeff V on Friday, November 28, 2008, 5 posts by 5 people.   Read the full thread at stackoverflow Discuss this with your friends on Facebook Answer Snippets (Read the full thread at stackoverflow): Estimates (most of my experience is with Xilinx, but it'll be similar for Altera and others): A raw that's the most accurate way to estimate logic utilization..

Best way to learn how to use FPGAs In next weeks probably I will have some little FPGA to play with. I have a programmer background (C, C++, Java mostly) and some (very) limited experience in electronics. What are the best tools to know if you want to develop on FPGAs? What are the best... Started by Myrrdyn on Monday, September 29, 2008, 17 posts by 17 people.   Read the full thread at stackoverflow Discuss this with your friends on Facebook Answer Snippets (Read the full thread at stackoverflow): There are lots of softwares available from Altera and Xilinx (2 big with tons of bus contention.... And Altera provide free tool chains that will allow you to build up programs for everything but their top syntax is pretty much like Pascal.

Best way to write to LUT based CPLD from slow CPU? Hi, I am inexperienced in CPLD design. I am using a slow CPU (PC ISA port) and LUT based CPLD (Altera MAX II) in my design. I implemented many control registers (implemented with D FF) in the CPLD that the CPU will write from time to time. The ISA bus... Started by VAX9000@gmail.com on Wednesday, March 11, 2009, 4 posts by 3 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): If you want to do this yourself for fun, then go for it! BTW, when. Need it, I could dig it up.

Going mad trying to solve PLL setup/hold timing violation issues in Quartus On 25 Nov 2009 00:45:49 GMT, Philip Pemberton <usenet09@philpem.me.uk Hi guys, I'm trying to generate a clock signal that can be switched between 16MHz, 8MHz and 4MHz, and have a 50% duty cycle (for a data separator/ slicer). Just to make this... Started by Philip Pemberton on Wednesday, November 25, 2009, 7 posts by 5 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): Ias Nial suggested, the way to do this is to use one (count them...one. But now I'm wondering if there's a better way do to compensate for it. Synchronisation FF, U2A), and eliminating the timing issue.

Searching for cost effective PCI express x1 core.. On Tue, 29 Sep 2009 09:24:18 +0200, "Morten Leikvoll" <mleikvol@yahoo.nospam ..using Altera Stratix3 and TI's XIO1011B PHY. Altera/PLDA's core is too expensive to use with a yearly fee. Axcon.dk have a nicer price, but I want to look for even better... Started by Morten Leikvoll on Tuesday, September 29, 2009, 7 posts by 5 people.   Read the full thread at omgili Discuss this with your friends on Facebook Answer Snippets (Read the full thread at omgili): BTW, the Arria II GX and Stratix IV GX contains PCIe hardmacros, wouldn't (the Statix3 was drawn in long time ago, but our Altera's dealer forgot to mention licensing cost;g1@enterpoint.co.uk We .... This is a possible way to go.